List of Accepted Papers and Posters

List of accepted papers

  • 24X-G3C5F6E3C3 (An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links)
  • 78X-G3D6G3A5B3 (Parka: Thermally Insulated Nanophotonic Interconnects)
  • 83X-B6J9P9D6F7 (Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC)
  • 23X-B6C2D8H8D4 (Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip)
  • 46X-B9P5P9A2C8 (Fault-tolerant Network-on-Chip based on Fault-aware Flits and Deflection Routing)
  • 65X-A4G6B6F3C9 (Highly Fault-tolerant NoC Routing with Application-aware Congestion Management)
  • 7X-J3P3P3D4D3 (Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence)
  • 9X-D6C2P3D7E2 (Highway in TDM NoCs)
  • 40X-H5F4A3P6P3 (On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck)
  • 3X-D3H2C7E3B8 (Unbiased Regional Congestion Aware Selection Function For NoCs)
  • 68X-A6F9J4G8F3 (A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips)
  • 6X-E3G2C3A3G3 (User Cooperation Network Coding Approach for NoC Performance Improvement)
  • 15X-D6G4E9D9C3 (Modeling and Design of High-Radix On-Chip Crossbar Switches)
  • 69X-G2D3G6F4F5 (Mathematical Modeling and Control of Multifractal Workloads for Data-Center-on-a-Chip Optimization)
  • 70X-P5B3F4A3J2 (Data Criticality in Network-On-Chip Design)
  • 72X-J3F5C3D8F4 (Improving DVFS in NoCs with Coherence Prediction)
  • 74X-C4B5B7J7C7 (Asymmetric NoC Architectures for GPU Systems)
  • 55X-G8G4G3F4C5 (MapPro - Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Network)

 
List of accepted posters

  • 2X-G6E4C3J8F3 (Proactive Wearout Decelerating Routing in Chip-Multiprocessor Interconnects)
  • 12X-A6A7D3B3C2 (ARTEMIS: An Aging-Aware Run-Time Application Mapping Framework for 3D NoC based Chip Multiprocessors)
  • 27X-G5C7B3A7D9 (Agate: A Cycle-accurate Power-gating Simulator for On-chip Networks)
  • 41X-C5J6B9C3B3 (Achievable Performance Enhancements with mm-Wave Wireless Interconnects in NoC)
  • 49X-J6A9D6J7P9 (Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design)
  • 50X-B2C9A2A3F7 (Dynamic network management for latency guarantees in on-chip networks)
  • 51X-C5A6D7B2A9 (Designing High-Performance, Power-Efficient NoCs With Embedded Silicon-in-Silica Nanophotonics)
  • 71X-H7J7B6E3A7 (Trigger Graphs for Fast and Accurate NoC Endpoint Simulation)